Dr. Anurag Srivastava

Inaugural Address
14th December 2012 10:40 AM

Dr. Anurag Srivastava is the Chief Technology Officer & Senior Vice President for Wipro’s Global IT Business. His responsibilities include technology strategy planning, technology incubation through Center’s of Excellence, business Innovation using futuristic technologies, technical stream & IP management, technology alliances in advanced areas with industry and academic forums.

Prior to this role, he was head of the Wipro Energy and Sustainability Services business. This business includes sustainability advisory, connected infrastructure & energy managed services to deliver comprehensive GHG reduction and energy cost optimization for our customers.

He was also responsible for starting the Consulting business for Wipro Infotech and supported its scale to the current level. He additionally led key strategic business transformational initiatives for Telecom, Telecom Equipment, Infrastructure, and Government industry verticals to build newer services/business models.

Dr. Anurag brings with him rich industry and business experience and depth of technology to Wipro. His areas of work experience are process & technology integration, data modeling & analytics, pattern recognition, distributed computing, Internet security and machine to machine collaboration. He has strong expertise in architectural frameworks, product life cycle management, incubation management and large transnational project management.

Prior to Wipro he has worked in IBM, Novell, HP-Verifone, Indian Institute of Science & Ness Technologies (Apar) in various technology & business leadership positions. He completed his PhD in Computer Science in the area of artificial intelligence and pattern recognition. He has several publications in international conferences and journals (IEEE SMC, Pattern Recognition and CC-AI). He holds a Bachelor’s in Electrical Engineering and Master’s in Computer Science & Engineering.

Dr. Anurag has been an invited speaker for various conferences by NASSCOM, Analysts fraternity, FICCI, CII, ASSOCHAM, Telematics, etc. and has several journal publications and articles.

Prof. John Walz

IEEE CS Keynote
14th December 2012 11:45 AM

John Walz, 2012 President of the IEEE Computer Society, retired from Lucent/AT&T with more than 25 years of software and systems engineering-management leadership experience as Senior Manager, Quality Strategy, for Lucent’s Supply Chain organization where he was responsible for developing and deploying Lucent’s quality management strategy for Lucent and its key suppliers. As a Senior IEEE member, he was Vice President of the Computer Society Technical & Conferences Activities Board, and First Vice President of Standards Activities Board, where his teams’ revised products and services to provide increased value to the Society’s members. He also serviced on the Society’s Vice Chair of Software and Systems Engineering Standards Executive Committee, Chair of Planning Committee, and Chair of Bylaws. His first IEEE volunteer role was on the COMPSAC conference.

Mr Walz has coauthored three books on the use of IEEE Computer Society software engineering standards to support CMMI, ISO 9001, and Lean Six Sigma. Walz received his electrical engineering degree, and MS from the Ohio State University.

He has extensive experience in implementing process improvement techniques, including ISO 9001, TL 9000, Baldrige National Quality Award criteria, Software Capability Maturity Model Integrated (CMMI), and IEEE Software Engineering Standards. He has experience in Business Process Management, Integrated Management Systems, Sarbanes-Oxley implementation and auditing, Software Assessments, Risk Management, and Information Technology (IT) process improvements. Mr. Walz is involved in standards development for ISO 9001, ISO 31000, TL 9000, and IEEE Software and Systems Engineering standards and participates in their committees.

Dr. Raj Jain

Invited Talk
Network Virtualization and Application Delivery Using Software Defined Networking
14th December 2012 12:30 PM

Raj Jain is a Fellow of IEEE, a Fellow of ACM, a winner of ACM SIGCOMM Test of Time award, CDAC-ACCS Foundation Award 2009, Hind Rattan 2011 award, and ranks among the top 70 in Citeseer's list of Most Cited Authors in Computer Science. Dr. Jain is currently a Professor of Computer Science and Engineering at Washington University in St. Louis. Previously, he was one of the Co-founders of Nayna Networks, Inc - a next generation telecommunications systems company in San Jose, CA. He was a Senior Consulting Engineer at Digital Equipment Corporation in Littleton, Mass and then a professor of Computer and Information Sciences at Ohio State University in Columbus, Ohio.

He is the author of "Art of Computer Systems Performance Analysis," which won the 1991 "Best-Advanced How-to Book, Systems" award from Computer Press Association. His fourth book entitled " High-Performance TCP/IP: Concepts, Issues, and Solutions," was published by Prentice Hall in November 2003. He has recently co-edited "Quality of Service Architectures for Wireless Networks: Performance Metrics and Management," published in April 2010.

Abstract:
Social networking, personalized searches, recommendation based online shopping, online banking, and other similar personalized services are extremely popular over the Internet today. Cloud computing provides unique opportunities for these Application Service Providers (ASPs) to manage and optimize their distributed computing resources. We present an open application delivery network architecture (OpenADN) which will allow any ASP to be able to optimize their user experience using a shared public WAN infrastructure in a multi-cloud environment, that is, multiple cloud computing facilities belonging to multiple cloud providers and private data centers. OpenADN extends software defined networking (SDN) which provides new opportunities for designing control architectures for networks by providing cleaner abstractions between the network control and data planes. Our extensions include several innovative techniques including control plane programmability using rule-based delegation, cross-layer communication, context routing, control/data plane separation, id/locator split, and application level flow-based routing to provide these services to ASPs.

Dr. Wolfgang Mueller

Invited Talk
Systems Prototyping and Virtualization – Current State and Future Directions
14th December 2012 04:30 PM

Wolfgang Mueller received his Diploma in Computer Science in 1989 and his doctorial degree in 1996 from the University of Paderborn. He is currently heading the Advanced Design Technologies group at C-LAB, a joint R&D lab of the University of Paderborn and Atos (formerly, Siemens Business Services).

Dr. Mueller is member of ACM and IEEE. Since 1989 he authored more than 150 national and international publications. He was/is member of various program and executive committees of various conferences and workshops. As such, he served as a program chair of the DATE 2010, for instance. His main interests focus on system design methodologies, languages, and integration technologies.

Abstract:
Virtualization is about the creation of virtual entities and environments and applied when physical resources are not available as required. In the context of IT technologies, such resources may be CPUs, networks, I/Os, storage devices, operating systems etc. As such, virtualization is also applied for server virtualization, like KVM, Xen, VMWare ESX, and Hyper-V, or during the design of electronic systems as virtual software development platforms, like QEMU, OVP, Simics, and CoMET.

In our presentation, we first give a general introduction to different IT virtualization technologies before we focus on platforms for virtual prototyping of electronic systems which provide considerably flexible and fast environments for early software development before the final hardware is available. More precisely, we introduce and investigate the open source software emulator QEMU with its underlying technologies and its different applications in the context of SystemC codesign and the development of embedded software. As such, we review different approaches for SystemC/QEMU cosimulation/emulation and the mutation-based testing of embedded software. The later includes the application of QEMU for testbench qualification. Finally, we give the example of a virtual prototyping platform for the development of closed-control loop software for an electric vehicle with conclusions for future directions.

Prof. Vinod Sharma

Distinguished Lecture
15th December 2012 10:45 AM

Prof. Vinod Sharma completed his B.Tech in 1978 from IIT Delhi and PhD in 1984 from CMU in Pittsburgh in Electrical Engg. He worked in Northeastern Univ in Boston and UCLA before joining Indian Institute of Science in 1988 where currently he is a Professor of Electrical Communication Engineering Department. He is on the editorial boards of the International Journal of Information and Coding theory, Inderscience, the Journal of electrical and Computer Engineering, Hindawi, and the International Journal of Advanced Computer Engineering, Serials Publications. Prof Sharma's research interests are in Wireless Communication, Information Theory and Communication Networks.

He is a Senior Member of the IEEE, a Fellow of the Institute of Electronics and Telecommunications Engineers (IETE),India and a Member of Institute of Mathematical Statistics.

Dr. Vinod Sharma is the winner of the ACCS-CDAC Foundation Award for 2012.

Prof. Santanu Chaudhury

Distinguished Lecture
Electronic Access for Print Content in Indian Languages
14th December 2012 02:15 PM

Dr. Santanu Chaudhury is currently a Schlumberger Chair Professor in the department of Electrical Engineering, IIT Delhi and was the Dean of UG Studies, IIT Delhi. He received his PhD in Computer Science and Engineering from IIT Kharagpur and a B.Tech in Electronics and Electrical Communication Engineering, IIT Kharagpur.

Prof. Santanu Chaudhury is an authority in the area of visual information processing and multimedia computing. He has developed a new approach for recognition of occluded 2D shapes, which had led to the development of new techniques for a variety of pattern recognition problems. The concept of mixed-category perception neural classifiers introduced by him and his collaborators was a novel concept with significant impact. A distinct line of approach for shape recognition using evolutionary algorithms emerged on the basis of his work. His was one of the earlier works to establish the advantage of using multiple neural classifiers for difficult biometric pattern recognition problems like signature recognition and this has led to a number of applications adapting the strategy proposed by him.

Dr. Chaudhury is a Fellow of Indian National Academy of Engineers, Indian National Academy of Sciences, Allahabad and was awarded Indian National Science Academy (INSA) medal for ‘Young Scientists’ in 1993.

Dr. Santanu Chaudhury is the winner of the ACCS-CDAC Foundation Award for 2012.

Abstract: Information processing in Indian languages is a requirement for true participative democracy in this country. Ability to access content in Indian languages through electronic access modalities is the key component for bridging the first level of digital divide. In this talk I shall focus on the problem of providing electronic access to the Indian language contents which are available to-day in hard-copy printed form. I shall discuss the challenges of developing character recognition system for Indian scripts. Technological innovations made for deploying Indian language OCR’s as web service will be described. Further, we shall consider the problem of developing search engine for a digital library of scanned books in Indian languages. Use of image based features, exploitation of noisy output of the character recognition system and indexing mechanisms will be discussed. My Talk will conclude with a vision of architecture of an integrated platform for information access in Indian languages.

Prof. R. Govindarajan

Invited Talk
Challenges & Opportunities in Heterogeneous Multi-Core Era
14th December 2012 05:15 PM

Prof. R. Govindarajan has been with SERC and the Department of Computer Science and Automation at IISc, Bangalore since 1995. He received a BSc in Mathematics from Madras University in 1981, and a BE in Electronics and Communication, and PhD in Computer Science from the Indian Institute of Science, Bangalore in 1984 and 1989, respectively.

He has held postdoctoral research fellowship and faculty positions at various Canadian universities and visiting faculty positions at US universities. His current research interests are in the areas of high performance computing, compilation techniques, and computer architecture. In these areas, he has more than 100 research publications in international journals and refereed conference proceedings. He is a senior member of the IEEE and a member of ACM and the IEEE Computer Society.

Abstract: Rapid advancements in multi-core processor architectures along with low-cost, low-latency, high-bandwidth interconnects have made clusters of multi-core machines a common resource in today's world. Combined with this, the recent advances witnessed in Graphics Processing Units provide excellent opportunity for exploiting large amounts of parallelism. In this talk I will discuss exploiting different types of parallelism in heterogeneous accelerator-based multi-core architectures. In particular we present our various work on compiling programs written in different languages (StreamIt, MATLAB, OpenMP, and X10) for GPU-based architectures. We proposes techniques to efficiently map applications for synergistic execution on CPU and GPU cores. We also propose novel techniques for automatic memory management to improve the ease of programming.

Mrittika Ganguli

Invited Talk
Hardware-based Intel® Virtualization Technology (Intel® VT)
15th December 2012 10:00 AM

Mrittika Ganguli is a Platform Software Architect in Intel’s Datacenter and Connected Systems Group. She has more than 16 years of experience in Software Systems design, development and Architecture. Her expertise at Intel lies in building the server system management architecture for cloud and server hardware deployed for cloud in datacenters. She has 4 approved patents in these areas and various published material in external journals.

Abstract: Hardware-based Intel® Virtualization Technology (Intel® VT)1 improves the fundamental flexibility and robustness of traditional software-based virtualization solutions by accelerating key functions of the virtualized platform, including:
- Speeding up the transfer of platform control between the guest operating systems (OSs) and the virtual machine manager (VMM)/hypervisor.
- Enabling the VMM to uniquely assign I/O devices to guest OSs.
- Optimizing the network for virtualization with adapter-based acceleration.

Virtualization is used in data centers for disaster recovery, high availability, and business continuity, and in desktops to increase flexibility, improve security, and reduce costs. Combining Intel® Trusted Execution Technology (Intel® TXT) with Intel VT creates a more secure, and protected virtualized platform for server and client deployments. Intel® TXT helps ensure the integrity of the virtual machine prior to launching an application. The foundation of enhanced cloud security will be built around the ability to 1) deliver secure multi-tenancy, 2) better protect data and enable compliance and 3) control access.

Isolate:A key premise for virtualized environments is that each virtual machine believes is a real machine, and has control over its physical and logical resources¬and as such it is “protected” from other systems/VMs. But the reality is that VMs are existing on shared resources and that software layers are responsible for arbitrating access to these shared resources and protecting the contents of one VM from another. With emerging attacks such as virtual rootkits and other VM escape methods and more scrutiny driven by the desire to move more critical workloads to the cloud, software-only approaches fall short. Intel VT and Intel TXT provide additional hardening to isolate workloads and system execution from launch through runtime, and helping to reduce overall attack surfaces of these shared environments.

Enforce:Knowing the computing environment is difficult in a cloud implementation¬the resources are abstracted away and may exist anywhere. But when considering deployment of critical workloads to the cloud¬or even to virtualized internal resources, one often MUST have more knowledge of the environment¬due to policy or regulatory conditions. TXT helps provide assurances of platform integrity through the enforcement of platform trust¬that a “known good” software environment is in control of the platform. With this knowledge, IT managers can establish and enforce policies such that critical workloads or sensitive data can only be deployed onto trusted platforms as a way to provide best protection of these apps.

Encrypt:Whenever physical control of data is reduced (such as putting data on laptops or storing in cloud), encryption is essential as the last line of defense to protect from misuse. For the cloud and other shared infrastructures, one wants to have encryption in place to protect data as it is moved to the cloud or between clouds and while in storage. Intel AES-NI provides performance benefits to make high-volume encryption faster and more efficient for these data transport and storage workloads. AES-NI also provides strengthening again side-channel attacks, which is an increasingly critical function in shared compute resources models.Combined, these help provide a more robust foundation to better address needs for security in data center and cloud deployments