Advanced Computing and Communications Society


1. Image Processing and Video Systems (On 16th December, 2012 [Full Day])
2. Agile System Development with Models (On 16th December, 2012 [Half Day])
3. Architectures for the Next Generation Internet and the Future Networks (On 16th December, 2012 [Half Day])

Image Processing and Video Systems

On 16th December, 2012 9:30 AM [Full Day]

This tutorial is structured in four parts, comprising basics of Image Processing leading up to popular Video Systems. The tutorial is conceptual and instructive covering basic concepts of Images that are used as building blocks in Video Systems. In particular it is covered as follows.

Part-1: Introduction to Images and Image Processing, covering basic ideas of Images, Image Analysis and Image processing both in Spatial and Frequency domain. 1.5 Hrs

Part-2: Introduction to Image Data Compression. The role of Image data compression as a critical requirement for building video systems is introduced. Image data compression in time (spatial) and Frequency domain is explained. Emphasis on Motion Compensation and DCT approaches is highlighted. 1.5 Hrs

Part-3:Image and Video Processing techniques and concepts are highlighted. Differences between plain Images and Video are explained. Important techniques and concepts that allow for efficient Image and Video Processing is emphasized. 1.5 Hrs

Part-4: This part shows how standard Video Systems like DVD and MPEG video streams is built out of simple image sequences and image data compression schemes. 1.5 Hrs

Tutorial Instructors:
Dr. Ashok Rao, Former Head, Network Project, CEDT, IISc, Bangalore


A Ph.D from EE Dept of IIT Bombay in the area of Signal Processing and Linear Algebra, he has over 25 years of Teaching, Research, Training and Consultancy work related to Signal Processing, Image & Video Processing, Multimedia and Applied Linear Algebra. His various training, consultancy and design assignments includes clients like, Texas Instruments, Analog Devices, Honeywell, Tektronics, SONY, SAGE Automation, NDS, Toshiba, SASKEN, LG, Robert Bosch, etc.

Dr. V. J. Harikrishna, Consultant

A Ph.D from EE Dept of IISc in the area of Signal & Image Processing and Linear Algebra, he has over 5 years of Training, Design and Consultancy work related to Signal Processing, Image & Video Processing, Statistical Signal Processing and Applied Linear Algebra. His various training and design assignments includes clients like, Tektronics, SONY, LG, Robert Bosch, etc.

Agile System Development with Models

Processor, SoC and System-of-Systems Modeling.

On 16th December, 2012 2:00 PM [Half Day]

Complex embedded systems are often developed by large teams spread across multiple locations around the globe. The range of roles and skillsets required to create such complex systems often spans multiple functions and disciplines. Roles include architects, designers, developers and test engineers. Often team members work on hardware, software and domain specific control design. Examples of domains include automotive, consumer electronic, aerospace, networking, high performance computing and storage.

Agile development using architectural models results in the creation of more effective globally optimized systems that are delivered to the market ahead of the competition. Hierarchical modeling supported by system design automation platforms helps hardware designers, software developers and domain experts create complex systems quickly using a shared model of the system under development.

In this tutorial, you will learn how to model different elements of a complex system such as processors and peripherals - in addition to modeling complete systems and system of systems. You will also see how models can be used to create prototypes, automate verification and create straight-through design flows for development of synthesizable RTL to realize hardware implementations using FPGAs or ASICs.

Tutorial contents :

Part 1) Theory - Processor Modeling and Verification

  • Architecture : ISA and MicroArchitecture
  • Elements of ISA
  • Architectural Modeling
  • An example with DLX
  • Your first SDK - Building Assembler and Linker
  • Agile Development -- Verifying Model with Line Translator
  • Modeling Registers and Memory Operands
  • Modeling Arithmetic and Logical Instructions
  • Attributes and Side Effects
  • Modeling Time Constraints
  • Building Processor Prototypes
  • Cycle Aware Simulation
  • Verification
  • The challenge of Verifying a Processor
  • Capturing Intent
  • Intent Driven Verification
  • Generate a Billion Tests With a Push of a Button !
  • Using Verification Specification Language to Constrain Test Space
  • Synthesizing Architecture Model to Synthesizable RTL (For FPGA or ASIC Development)
  • The Future of Electronic Embedded Systems Development

Part 2) Applications - Embedded Systems Modeling

  • Elements of System
  • Models, Components and Relations
  • Creating A Simple System Model
  • Creating a Simple Device (Peripheral) Model
  • Building Prototyping Platforms from System Model
  • Introduction To System-of-Systems Modeling
  • Domain Models, Software Models, Hardware Models
  • System-of-System Exploration with System Prototyping Platforms
  • Examples: Automotive Multi-ECU Network Model (CAN Bus)
  • Examples; Aerospace Multi-Node Computer Network Model (MIL STD 1553)
  • The Future of Electronic Embedded Systems Development

About EdVantage
EdVantage offers specialized education solutions to professionals for learning embedded design skills and consulting services to organizations for setting up centers of excellence in embedded design.
For inquiries please visit or contact

Tutorial Instructor:
Gopi Kumar Bulusu


Gopi Kumar Bulusu is the founder member and CEO at Sankhya Technologies Private Limited. He is an acknowledged expert in the areas of distributed computing and embedded systems. His team received the Lockheed Martin India Innovation award in the year 2008 and the DST-Lockheed Martin Innovation award during 2009. He holds 4 granted US patents in addition to several pending patent applications.

He is a regular speaker at industry and academic events on a wide range of topics. Gopi is an active member of IEEE and presently serves as the SubSection chair for the IEEE Vizag-Bay SubSection. He is a member on the editorial advisory board, EETimes India. His key interests are in the areas of creating innovative platforms that bring the power and efficiency of architectural model driven solutions to IT system designers and business users. On a higher plane, Gopi Bulusu believes in applying the benefits of innovation and technology to promote national prosperity -- he is a founding member of Gravity2.0 - The Regional Planning and Development Forum and Supercomputing Consortium of India.

Prior to 1996, he was a senior software engineer in the embedded software division of Mentor Graphics Corporation, where he was a member of a core team that created one of the industry's first C++ compilers for Motorola 68k processors. Gopi's work at Mentor resulted in 2 US patents. He holds 4 granted US patents in addition to several pending patent applications.

Architectures for the Next Generation Internet and the Future Networks

On 16th December, 2012 9:30 AM [Half Day]

This tutorial on latest advances in future networking architectures is designed for researchers, engineers and managers involved in future networking product strategies. Networking research funding agencies in USA, Europe, Japan, and other countries are encouraging research on revolutionary architectures that may or may not be bound by the restrictions of the current TCP/IP based Internet. We present an overview of a number of such research projects and activities in this direction. The topics covered include: Clean-Slate Research Programs, Virtualization, Software Defined Networking, ID-Locator Separation, Content Centric Networking, and OpenFlow.

Target Audience:
Engineers, managers, and academic personnel, who want to keep track of the latest developments in networking, will find the information useful. Networking researchers all over the world are busy developing new architectures and test beds. There is significant interest in the industry and military on these developments

Detailed Outline of Topics Covered:

  • Future Internet Projects
    • Why to worry about Future Internet?
    • Key Problems with Current Internet
    • Names, IDs, Locators
  • Future Internet: Areas of Research
  • Five Trends in Networking
    • Trend 1: Moore’s Law
    • Trend 2: Multihoming + Mobility
    • Trend 3: Wireless Edge
    • Trend 4: Declining Revenues in Transport
    • Trend 5: Profusion of Services
  • Internet 3.0
    • Internet 3.0: Next Generation Internet
    • Internet Generations
    • Service Center Evolution
    • Globally Distributed Services
    • Trend: Private Smart WANs
    • Open ADN
    • Ten Key Features that Services Need
    • Five Arch Design Principles for Success
    • Networking: Failures vs Successes
    • Five Architecture Design Principles
    • The Narrow Waist
  • Content Centric Networks
    • Content-Centric Networks
    • CCN Packets
    • CCN Capable Routers Operation
    • CCN Security
    • VOIP over CCN
  • Routing Architectures: OpenFlow
    • Reactive and Proactive Operation
    • Flow-based vs. Aggregated
    • Current Limitations of OpenFlow
  • Software Defined Networks
    • Problem: Complex Routers
    • Solution: Divide, Simplify and Standardize
    • Multi-Tenant SDN Architecture
    • SDN Architecture Component Examples
    • SDN Abstractions
    • SDN Impact
  • ID-Locator Split
    • HIP
  • Next Generation Testbeds
    • GENI
    • FIRE
    • AKARI Components
  • NSF FIA Winners
    • XIA
    • MobilityFirs
    • NEBULA

Tutorial Instructors:


Raj Jain is a Fellow of IEEE, a Fellow of ACM, A Fellow of AAAS, a winner of ACM SIGCOMM Test of Time award, CDAC-ACCS Foundation Award 2009. Dr. Jain is currently a Professor of Computer Science and Engineering at Washington University in St. Louis. Previously, he was one of the Co-founders of Nayna Networks, Inc - a next generation telecommunications systems company in San Jose, CA. He was a Senior Consulting Engineer at Digital Equipment Corporation in Littleton, Mass and then a professor of Computer and Information Sciences at Ohio State University in Columbus, Ohio.

He is the author of ``Art of Computer Systems Performance Analysis,'' which won the 1991 ``Best-Advanced How-to Book, Systems'' award from Computer Press Association. His fourth book entitled " High-Performance TCP/IP: Concepts, Issues, and Solutions," was published by Prentice Hall in November 2003. He is co-editor of "Quality of Service Architectures for Wireless Networks: Performance Metrics and Management," published in February 2010.

Further information about Dr. Jain including all his publications can be found at