Sakina Pitalwala

Assisted chip-design in the era of Large Language Models

Abstract
Over the years, the chip design process has seen a surge of AI-powered applications that have optimized design workflows, reduced time-to-market, and streamlined engineering efforts. Concurrently, the remarkable advancements in large language models (LLMs) for natural language processing tasks have inspired researchers to explore their potential in adjacent domains which have similarities with natural language, like code. The impressive performance of LLMs in software-development tasks, including code generation, review, and debugging, has naturally led to investigations into their applicability to the hardware development domain as well. In this talk, we seek to shed light on the transformative potential of large language models in streamlining and enhancing the complex chip design process, ultimately contributing to the continued advancements in hardware development.

Bio
I’m an AI Applied Research Scientist at Intel with over 8 years of experience. For the past 5 years at Intel, I’ve developed AI solutions for areas like platform security, Intel product design and validation, IT operations, and sales and marketing. My main interests in AI are classical machine learning, advanced natural language processing, and generative AI. Outside of work, I enjoy painting and embroidery, which give me a creative balance to my tech-focused work. Know more

Sakina Pitalwala
Intel